1. Field of the Invention
The present invention relates to hardware circuit emulation. In particular, the present invention relates to providing a logic signal transition trace ("waveform") for any internal net in a device under emulation.
2. Discussion of the Related Art
In hardware emulation, a logic design is compiled for implementation in a "bread board" of field programmable logic elements (e.g., field programmable gate arrays or FPGAs). FIG. 1 is a simplified block diagram illustrating a hardware circuit emulator 100. As shown in FIG. 1, circuit emulator 100, which is typically under control of a host computer or "workstation" 101 (not shown), includes (a) a user logic design portion 102 for implementing the device under emulation, and (b) a probe portion 103 for receiving and routing selected internal signals of user logic design portion 101 to a logic analyzer interface 104. Typically, user logic design portion 102 and probe portion 103 are implemented by configuring the bread board of FPGAs, with each FPGA in user logic design portion 102 providing a small number of signals (e.g., two signals per FPGA) over a "probe bus" 106 to a probe FPGA in probe portion 103. The primary input and output signals of user design portion 102 and the probe output signals of probe portion 103 are provided to logic analyzer interface 104 for access by a logic analyzer 105.
For a large design (e.g., a million gates), the number of internal nodes or nets that can be monitored during emulation through the mechanism of FIG. 1 is limited by (i) the number of signals that can be routed between user design portion 102 to probe portion 103, (ii) the available number of signals in logic analyzer interface 104, and (iii) the amount of memory in logic analyzer 105. The number of signals that can be routed between user design portion 102 and probe portion 103, and in logic analyzer interface 104 can be increased using the "virtual wire" technique. An example of the virtual wire technique is disclosed in a copending patent application, entitled "Circuit Partitioning Technique for use with Multiplexed Interconnection" by Anant Agarwal et al., Ser. No. 08/588,649, filed Jan. 19, 1996 now U.S. Pat. No. 5,854,752 issued on Dec. 29, 1998 and assigned to IKOS Systems, Cupertino, Calif., which is also the Assignee of the present application. The disclosure of 08/588,649 Application is hereby incorporated by reference in its entirety. However, to increase the amount of memory in a logic analyzer is costly, since very fast memory components are used in a logic analyzer.
Under the virtual wire technique, time in emulator 100 is discretized to a "virtual clock" (vclk) signal, which is typically many times the frequency of the clock signals of the design under emulation. The vclk signal allows multiple signals routed between FPGAs to time-share an input/output pin. Multiplexing of signals is accomplished by synthesizing additional logic circuits in each FPGA. Using this technique, for example, if 10 signals share each single input/output pin, and if logic analyzer interface 104 includes 192 wires, then over 1900 signals from user design portion 102 can be routed through probe portion 103 to logic analyzer 105. However, for a large design, the number of signals that can be routed to logic analyzer 105 represents a very small percentage of the total number of nets.
Since the number of nets that can be examined by logic analyzer 105 represents a very small percentage of all nets in a large design, the designer must specifically select, prior to the emulation, which of the nets are to be examined by logic analyzer 105. Any net not selected cannot be reexamined without resynthesizing the emulator model of the design. The typical process flow is illustrated by flow diagram 200 of FIG. 2. As shown in FIG. 2, a design netlist (indicated by reference numeral 202) is downloaded into a modeling engine 205. (A modeling engine can be an emulator or a simulator). At the same time, the user (indicated by reference numeral 201) specifies a list of desired signals to be examined by modeling engine 205 (e.g., input signals, state variables in the design netlist, and selected internal signals) before modeling can begin in modeling engine 205. As the modeling process progresses, a logic trace (indicated by reference numeral 203) is provided for each signal in the list of desired signals. A conventional waveform tool 204 can then access the saved logic trace to retrieve the waveform of the desired signals. Under this approach, to retrieve the waveform of any signal not included in the initial list of desired signals, process 200 must be re-run. Further, while re-running process 200 is cumbersome and time-consuming in a simulation environment, re-running process 200 in an emulator may be impossible since some "real-world" input stimuli may not be readily reproducible.